MA320002【PDF 60/208 页】MODULE PLUG-IN PIC32 USB OTG

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Sheet目录1227

56页 57页 58页 59页 [60页]61页 62页 63页 64页

TABLE 4-13:

ADC REGISTERS MAP

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

9000 AD1CON1 (1)

31:16

15:0

—

ON

—

FRZ

—

SIDL

—

—

—

—

—

—

FORM<2:0>

—

—

—

SSRC<2:0>

—

—

CLRASAM

—

—

—

ASAM

—

SAMP

—

DONE

0000

0000

9010 AD1CON2 (1)

9020 AD1CON3 (1)

31:16

15:0

31:16

15:0

—

VCFG2

—

ADRC

—

VCFG1

—

—

—

VCFG0

—

—

—

OFFCAL

—

—

—

—

—

CSCNA

—

SAMC<4:0>

—

—

—

—

—

—

—

BUFS

—

—

—

—

—

—

— —

SMPI<3:0>

— —

ADCS<7:0>

—

—

—

BUFM

—

—

ALTS

—

0000

0000

0000

0000

9040 AD1CHS (1)

31:16

15:0

CH0NB

—

—

—

—

—

—

—

—

CH0SB<3:0>

— —

—

CH0NA

—

—

—

—

—

—

—

—

CH0SA<3:0>

— —

—

0000

0000

9060 AD1PCFG (1)

9050 AD1CSSL (1)

31:16

15:0

31:16

15:0

—

PCFG15

—

CSSL15

—

PCFG14

—

CSSL14

—

PCFG13

—

CSSL13

—

PCFG12

—

CSSL12

—

PCFG11

—

CSSL11

—

PCFG10

—

CSSL10

—

PCFG9

—

CSSL9

—

PCFG8

—

CSSL8

—

PCFG7

—

CSSL7

—

PCFG6

—

CSSL6

—

PCFG5

—

CSSL5

—

PCFG4

—

CSSL4

—

PCFG3

—

CSSL3

—

PCFG2

—

CSSL2

—

PCFG1

—

CSSL1

—

PCFG0

—

CSSL0

0000

0000

0000

0000

9070 ADC1BUF0

9080 ADC1BUF1

9090 ADC1BUF2

90A0 ADC1BUF3

90B0 ADC1BUF4

90C0 ADC1BUF5

90D0 ADC1BUF6

90E0 ADC1BUF7

90F0 ADC1BUF8

9100 ADC1BUF9

31:16

15:0

31:16

15:0

31:16

15:0

31:16

15:0

31:16

15:0

31:16

15:0

31:16

15:0

31:16

15:0

31:16

15:0

31:16

15:0

ADC Result Word 0 (ADC1BUF0<31:0>)

ADC Result Word 1 (ADC1BUF1<31:0>)

ADC Result Word 2 (ADC1BUF2<31:0>)

ADC Result Word 3 (ADC1BUF3<31:0>)

ADC Result Word 4 (ADC1BUF4<31:0>)

ADC Result Word 5 (ADC1BUF5<31:0>)

ADC Result Word 6 (ADC1BUF6<31:0>)

ADC Result Word 7 (ADC1BUF7<31:0>)

ADC Result Word 8 (ADC1BUF8<31:0>)

ADC Result Word 9 (ADC1BUF9<31:0>)

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

Legend:

Note 1:

x = unknown value on Reset, — = unimplemented, read as ‘ 0 ’. Reset values are shown in hexadecimal.

This register has corresponding CLR, SET and INV Registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.

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